Introduction to RISC-V Interrupts

Interrupts in RISC-V are governed by standards and specification. Each RISC-V core's interrupt generation and handling process should be compliant to the specification. This course discusses the following:a. Privilege Levels in RISC-Vb. Traps in RISC-Vc. Platform Level Interrupt Controller (PLIC) Specificationd. Compares PLIC Implementation on FE310 SoC to Spece. Control and Status Registers (CSRs) f. Instructions to read and write CSRs in RISC-Vg. Configuring GPIO peripheral in FE310 SoCh. Configuring PLIC to allow GPIO interrupti. Configure MIE & MSTATUS CSRs on the core  to enable machine mode interrupts and machine mode external interruptsj. Installation of GNU tools (compilers, OpenOCD)k. Test application in assembly to blink blue LED on Hifive1-Rev B board.Students who enrol would be taken through a journey starting from basics of what are interrupts, exceptions and traps in RISC-V, followed by PLIC standard discussing the parameters, how to configure those parameters on PLIC to generate interrupt and claiming and completing the interrupt handling process and finally on writing an test application to blink LED. The major exercise and focus on this course is on writing RISC-V assembly code, assembling & linking with GNU tools, generating ELF, and programming it on Hifive1-RevB board to blink blue LED on board. Update on Sept 5, 2024: Corrected the memory map address for Context1 Threshold, Claim and enable registers and attached as pdf for Section 3, Lecture 7. The PLIC specification pdf too is attached for reference.